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| M58BW16F M58BW32F 16 or 32 Mbit (x 32, boot block, burst) 3.3 V supply Flash memories Preliminary Data Features Supply voltage - VDD = 2.7 V to 3.6 V (45 ns) or VDD = 2.5 V to 3.3 V (55 ns) - VDDQ = VDDQIN = 2.4 V to 3.6 V for I/O buffers High performance - Access times: 45 and 55 ns - Synchronous burst reads - 75 MHz effective zero wait-state burst read - Asynchronous page reads M58BW32F memory organization: - Eight 64 Kbit small parameter blocks - Four 128 Kbit large parameter blocks - Sixty-two 512 Kbit main blocks M58BW16F memory organization: - Eight 64 Kbit parameter blocks - Thirty-one 512 Kbit main blocks Hardware block protection - WP pin to protect any block combination from Program and Erase operations - PEN signal for Program/Erase Enable Irreversible modify protection (OTP like) on 128 Kbits: - Block 1 (bottom device) or block 72 (top device) in the M58BW32F - Blocks 2 and 3 (bottom device) or blocks 36 and 35 (top device) in the M58BW16F Security - 64-bit unique device identifier (UID) Fast programming - Write to buffer and program capability Optimized for FDI drivers - Common Flash interface (CFI) - Fast Program/Erase Suspend feature in each block Low power consumption - 100 A typical Standby current PQFP80 (T) LBGA LBGA80 (ZA) 10 x 8 ball array Electronic signature - Manufacturer code: 0020h - Top device codes: M58BW32FT: 8838h M58BW16FT: 883Ah - Bottom device codes: M58BW32FB: 8837h M58BW16FB: 8839h Automotive device grade 3: - Temperature: -40 to 125 C - Automotive grade certified March 2008 Rev 5 1/87 www.numonyx.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents M58BW16F, M58BW32F Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset/Power-down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Enable (PEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Burst Address Advance (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Valid Data Ready (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output supply voltage (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input supply voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ground (VSS and VSSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Don't use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Not connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . 24 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . 25 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/87 M58BW16F, M58BW32F 3.1.7 3.1.8 Contents Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset/Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Synchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 3.2.2 Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 Read Select bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Standby Disable bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 X-Latency bits (M13-M11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Y-Latency bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Valid Data Ready bit (M8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Wrap Burst bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Burst Length bit (M2-M0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 38 Set Block Protection Configuration Register command . . . . . . . . . . . . . . 38 Clear Block Protection Configuration Register command . . . . . . . . . . . . 38 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 5.2 5.3 5.4 Program/Erase Controller Status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Erase Suspend Status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Erase Status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program/Write to Buffer and Program Status (bit 4) . . . . . . . . . . . . . . . . . 42 3/87 Contents M58BW16F, M58BW32F 5.5 5.6 5.7 5.8 PEN Status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program Suspend Status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Block Protection Status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 7 8 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Appendix A Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4/87 M58BW16F, M58BW32F List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58BW32F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M58BW32F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M58BW16F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M58BW16F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronous Burst Read Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Asynchronous Bus Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Asynchronous Page Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous Write and Latch controlled Write AC characteristics . . . . . . . . . . . . . . . . . . 54 Synchronous Burst Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power supply AC and DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset, Power-down and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LBGA80 10 x 12 mm - 8 x 10 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PQFP80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 66 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CFI - Query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 M58BW16F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M58BW16F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 M58BW32F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5/87 List of figures M58BW16F, M58BW32F List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Asynchronous Latch Controlled Bus Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 48 Asynchronous Chip Enable Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . 49 Asynchronous Address Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . 49 Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous Latch controlled Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Synchronous Burst Read, Latch Enable controlled (data valid from 'n' clock rising edge) . 55 Synchronous Burst Read, Chip Enable controlled (data valid from 'n' clock rising edge) . 56 Synchronous Burst Read, Valid Address transition controlled (data valid from 'n' clock rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Synchronous Burst Read (data valid from 'n' clock rising edge). . . . . . . . . . . . . . . . . . . . . 58 Synchronous Burst Read - valid data ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Power supply slope specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset, Power-down and Power-up AC waveforms - Control pins Low. . . . . . . . . . . . . . . . 62 Reset, Power-down and Power-up AC waveforms - Control pins toggling. . . . . . . . . . . . . 62 LBGA80 10 x 12 mm - 8 x 10 ball array, 1 mm pitch, bottom view package outline . . . . . 64 PQFP80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 66 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 69 Block Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power-up sequence followed by Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . 72 Command interface and Program/Erase controller flowchart (a) . . . . . . . . . . . . . . . . . . . . 73 Command interface and Program/Erase controller flowchart (b) . . . . . . . . . . . . . . . . . . . . 74 Command interface and Program/Erase controller flowchart (c) . . . . . . . . . . . . . . . . . . . . 75 Command interface and Program/Erase controller flowchart (d) . . . . . . . . . . . . . . . . . . . . 76 Command interface and Program/Erase controller flowchart (e) . . . . . . . . . . . . . . . . . . . . 77 6/87 M58BW16F, M58BW32F Description 1 Description The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a double-word basis using a 2.7 V to 3.6 V or 2.5 V to 3.3 V VDD supply for the circuit and a 2.4 V to 3.6 V VDDQ supply voltage for the input and output buffers. In the rest of the document the M58BW16F and M58BW32F will be referred to as M58BWxxF unless otherwise specified. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read interface allows a high data transfer rate controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All write operations are asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture: The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW32FT) or at the bottom (M58BW32FB) of the address space. The first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. The memory array organization is detailed in Table 2: M58BW32F top boot block addresses and Table 3: M58BW32F bottom boot block addresses. The M58BW16F has an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW16FT the parameter blocks are located at the top of the address space whereas in the M58BW16FB, they are located at the bottom. The memory array organization is detailed in Table 4: M58BW16F top boot block addresses and Table 5: M58BW16F bottom boot block addresses. Program and Erase commands are written to the command interface of the memory. An onchip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block, and then resumed. Program can be suspended to Read data in any other block, and then resumed. Each block can be programmed and erased over 100,000 cycles. 7/87 Description M58BW16F, M58BW32F All blocks are protected during power-up. The M58BWxxF features five different levels of hardware and software block protection to avoid unwanted Program/Erase operations: Write/Protect Enable input, WP, hardware protects a combination of blocks from Program and Erase operations. The blocks to be protected are configured individually by issuing a Set Block Protection Configuration Register or a Clear Block Protection Configuration Register command. All Program or Erase operations are blocked when Reset, RP, is held Low. A Program/Erase Enable input, PEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. A permanent user-enabled protection against Modify operations is available: - - on one specific 128-Kbit parameter block in the M58BW32F - block 1 for bottom devices or block 72 for top devices on two specific 64-Kbit parameter blocks in the M58BW16F - blocks 2 and 3 for bottom devices or blocks 36 and 35 for top devices. A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is reduced to the standby level, the device is write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer code and a device code are available. They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. Finally, the M58BWxxF features a 64-bit unique device identifier (UID) which is programmed by Numonyx on the production line. It is unique for each die and can be used to implement cryptographic algorithms to improve security. Information is available in the CFI area (see Table 32: M58BW16F extended query information). The memory is offered in PQFP80 (14 x 20 mm) and LBGA80 (1.0 mm pitch) packages and it is supplied with all the bits erased (set to '1'). 8/87 M58BW16F, M58BW32F Figure 1. Logic diagram VDD VDDQ VDDQIN Description A0-Amax(1) E K PEN L RP G GD W WP B M58BW16F M58BW32F DQ0-DQ31 R VSS VSSQ AI13224b 9/87 Description Table 1. Signal names Function Address inputs Data input/output, command input Data input/output, Burst Configuration Register Data input/output Burst Address Advance input Chip Enable input Output Enable input Burst Clock input Latch Enable input Valid Data Ready output Reset/Power-down input Write Enable input Output Disable input Write Protect input Supply voltage Power supply for output buffers Power supply for input buffers only Program/Erase Enable Ground Input/output ground Not connected internally Don't use as internally connected M58BW16F, M58BW32F Signal name A0-Amax(1) DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 B E G K L R RP W GD WP VDD VDDQ VDDQIN PEN VSS VSSQ NC DU Direction Inputs I/O I/O I/O Input Input Input Input Input Output Input Input Input Input Input 1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. 10/87 M58BW16F, M58BW32F Figure 2. LBGA connections (top view through package) Description 1 2 3 4 5 6 7 8 A A15 A14 VDD PEN VSS A6 A3 A2 B A16 A13 A12 A9 A8 A5 A4 A1 C A17 A18 A11 A10 NC A7 NC A0 D DQ3 DQ0 A19/ NC(1) NC NC DQ31 DQ30 DQ29 E VDDQ DQ4 DQ2 DQ1 DQ27 DQ28 DQ26 VDDQ F VSSQ DQ7 DQ6 DQ5 NC DQ25 DQ24 VSSQ G VDDQ DQ8 DQ10 DQ9 DQ22 DQ21 DQ23 VDDQ H DQ13 DQ12 DQ11 WP DQ17 DQ19 DQ18 DQ20 J DQ15 DQ14 L B E G R DQ16 K VDDQIN RP K VSS VDD W GD NC AI12854b 1. Ball D3 is NC in the M58BW16F and A19 in the M58BW32F. 11/87 Description Figure 3. PQFP connections (top view through package) M58BW16F, M58BW32F 80 73 65 DU R GD WP W G E VDD B VSS L NC NC K RP VDDQIN 25 32 A3 A4 A5 A6 A7 A8 VSS PEN VDD A9 A10 A11 A12 A13 A14 A15 40 DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DU A0 A1 A2 1 64 12 M58BW16F M58BW32F 53 24 41 DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 A19/NC(1) A18 A17 A16 AI13225b 12/87 M58BW16F, M58BW32F Description 1.1 Block protection The M58BWxxF features four different levels of block protection. Write Protect pin, WP, - When WP is Low, VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. Any combination of blocks is possible. Any attempt to program or erase a protected block will return an error in the Status Register (see Table 13: Status Register bits). Reset/Power-down pin, RP, - If the device is held in reset mode (RP at VIL), no Program or Erase operation can be performed on any block. Program/Erase Enable, PEN, - The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register. Permanent protection against modify operations - specific OTP-like blocks can be permanently protected against modify operations (Program/Erase): - - in the M58BW32F, a unique 128-Kbit parameter block - block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices in the M58BW16F, two 64-Kbit parameter blocks - blocks 2 and 3 (01000h01FFFh) for bottom devices or blocks 36 and 35 (7E000h-7EFFFh) for top devices This protection is user-enabled. Details of how this protection is activated are provided in a dedicated application note. After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. All blocks are protected at power-up. 13/87 Description Table 2. # 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 M58BW16F, M58BW32F M58BW32F top boot block addresses Size (Kbit) 128 128 128 128 64 64 64 64 64 64 64 64 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address range(1) FF000h-FFFFFh FE000h-FEFFFh(2) FD000h-FDFFFh FC000h-FCFFFh FB800h-FBFFFh FB000h-FB7FFh FA800h-FAFFFh FA000h-FA7FFh F9800h-F9FFFh F9000h-F97FFh F8800h-F8FFFh F8000h-F87FFh F4000h-F7FFFh F0000h-F3FFFh EC000h-EFFFFh E8000h-EBFFFh E4000h-E7FFFh E0000h-E3FFFh DC000h-DFFFFh D8000h-DBFFFh D4000h-D7FFFh D0000h-D3FFFh CC000h-CFFFFh C8000h-CBFFFh C4000h-C7FFFh C0000h-C3FFFh BC000h-BFFFFh B8000h-BBFFFh B4000h-B7FFFh B0000h-B3FFFh AC000h-AFFFFh A8000h-ABFFFh A4000h-A7FFFh A0000h-A3FFFh 9C000h-9FFFFh 98000h-9BFFFh 94000h-97FFFh 90000h-93FFFh 14/87 M58BW16F, M58BW32F Table 2. # 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description M58BW32F top boot block addresses (continued) Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address range(1) 8C000h-8FFFFh 88000h-8BFFFh 84000h-87FFFh 80000h-83FFFh 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 00000h-03FFFh 1. Addresses are indicated in 32-bit addressing. 2. OTP block. 15/87 Description Table 3. # 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 M58BW16F, M58BW32F M58BW32F bottom boot block addresses Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address range(1) FC000h-FFFFFh F8000h-FBFFFh F4000h-F7FFFh F0000h-F3FFFh EC000h-EFFFFh E8000h-EBFFFh E4000h-E7FFFh E0000h-E3FFFh DC000h-DFFFFh D8000h-DBFFFh D4000h-D7FFFh D0000h-D3FFFh CC000h-CFFFFh C8000h-CBFFFh C4000h-C7FFFh C0000h-C3FFFh BC000h-BFFFFh B8000h-BBFFFh B4000h-B7FFFh B0000h-B3FFFh AC000h-AFFFFh A8000h-ABFFFh A4000h-A7FFFh A0000h-A3FFFh 9C000h-9FFFFh 98000h-9BFFFh 94000h-97FFFh 90000h-93FFFh 8C000h-8FFFFh 88000h-8BFFFh 84000h-87FFFh 80000h-83FFFh 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 16/87 M58BW16F, M58BW32F Table 3. # 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description M58BW32F bottom boot block addresses (continued) Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 64 64 64 64 64 64 64 64 128 128 128 128 Address range(1) 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 07800h-07FFFh 07000h-077FFh 06800h-06FFFh 06000h-067FFh 05800h-05FFFh 05000h-057FFh 04800h-04FFFh 04000h-047FFh 03000h-03FFFh 02000h-02FFFh 01000h-01FFFh(2) 00000h-00FFFh 1. Addresses are indicated in 32-bit word addressing. 2. OTP block. 17/87 Description Table 4. # 38 37 36(1) 35(1) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1. OTP block. M58BW16F, M58BW32F M58BW16F top boot block addresses Size (Kbit) 64 64 64 64 64 64 64 64 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address range 7F800h-7FFFFh 7F000h-7F7FFh 7E800h-7EFFFh 7E000h-7E7FFh 7D800h-7DFFFh 7D000h-7D7FFh 7C800h-7CFFFh 7C000h-7C7FFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 00000h-03FFFh 18/87 M58BW16F, M58BW32F Table 5. # 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3(1) 2(1) 1 0 1. OTP block. Description M58BW16F bottom boot block addresses Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 64 64 64 64 64 64 64 64 Address range 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 03800h-03FFFh 03000h-037FFh 02800h-02FFFh 02000h-027FFh 01800h-01FFFh 01000h-017FFh 00800h-00FFFh 00000h-007FFh 19/87 Signal descriptions M58BW16F, M58BW32F 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-Amax) Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. Chip Enable must be Low when selecting the addresses. The Address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a Read operation. The Address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is Low, VIL. The address is internally latched in an Erase or Program operation. 2.2 Data inputs/outputs (DQ0-DQ31) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the command interface of the Program/Erase controller. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both Low, VIL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection Configuration Register, the CFI information or the contents of Burst Configuration Register or Status Register. The data bus is high impedance when the device is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/Power-down at VIL. The Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at VIL. 2.3 Chip Enable (E) The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the standby level. 2.4 Output Enable (G) The Output Enable, G, gates the outputs through the data output buffers during a Read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable. 20/87 M58BW16F, M58BW32F Signal descriptions 2.5 Output Disable (GD) The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. 2.6 Write Enable (W) The Write Enable, W, input controls writing to the command interface, input address and data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). 2.7 Reset/Power-down (RP) The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the command interface and the Program/Erase controller are reset. The Status Register information is cleared and power consumption is reduced to the standby level (IDD1). The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-down goes High, VIH, the memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after tPHWL. If Reset/Power-down goes Low, VIL, during a Block Erase or a Program operation, the internal state machine handles the operation as a Program/Erase Suspend, so the maximum time defined inTable 12: Program, Erase times and endurance cycles must be applied. During power-up power should be applied simultaneously to VDD and VDDQIN with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate the Reset/Power-down pin, RP, with the reset signal of the microprocessor. Otherwise, if a Reset operation occurs while the memory is performing an Erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read mode. See Table 24 and Figure 22: Reset, Power-down and Power-up AC waveforms - Control pins Low, for more details. 2.8 Program/Erase Enable (PEN) The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register. 21/87 Signal descriptions M58BW16F, M58BW32F 2.9 Latch Enable (L) The Bus Interface can be configured to latch the Address inputs on the rising edge of Latch Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations. 2.10 Burst Clock (K) The Burst Clock, K, is used to synchronize the memory with the external bus during Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge when Latch Enable is Low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous Bus Operations the Clock is not used. 2.11 Burst Address Advance (B) The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data inputs/outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B, may be tied to VIL. 2.12 Valid Data Ready (R) The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active. 2.13 Write Protect (WP) The Write Protect, WP, provides protection against Program or Erase operations. When Write Protect, WP, is at VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. Program and Erase operations to protected blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used. 22/87 M58BW16F, M58BW32F Signal descriptions 2.14 Supply voltage (VDD) The supply voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the Program/Erase controller. 2.15 Output supply voltage (VDDQ) The output supply voltage, VDDQ, is the output buffer power supply for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs. 2.16 Input supply voltage (VDDQIN) The input supply voltage, VDDQIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0-Amax and DQ0-DQ31, when used as inputs. 2.17 Ground (VSS and VSSQ) The ground VSS is the reference for the internal supply voltage VDD. The ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1 F capacitor should be connected between the supply voltages, VDD, VDDQ and VDDQIN and the grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 18: DC characteristics, for maximum current supply requirements. 2.18 Don't use (DU) This pin should not be used as it is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected. 2.19 Not connected (NC) This pin is not physically connected to the device. 23/87 Bus operations M58BW16F, M58BW32F 3 Bus operations Each bus operations that controls the memory is described in this section, see tables 6 and 7 Bus operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write. No synchronous operation can be performed until the Burst Control Register has been configured. The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Asynchronous Bus operations For asynchronous bus operations refer to Table 6 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL. 3.1.1 Asynchronous Bus Read Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Block Protection Configuration Register, Status Register, CFI and Burst Configuration Register) in the command interface. A valid bus operation involves setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data inputs/outputs will output the value, see Figure 7: Asynchronous Bus Read AC waveforms, and Table 19: Asynchronous Bus Read AC characteristics, for details of when the output becomes valid. Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-down. 3.1.2 Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address inputs, setting Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address inputs can change. Set Output Enable Low, VIL, to read the data on the Data inputs/outputs; see Figure 8: Asynchronous Latch Controlled Bus Read AC waveforms and Table 19: Asynchronous Bus Read AC characteristics, for details on when the output becomes valid. Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation. 24/87 M58BW16F, M58BW32F Bus operations 3.1.3 Asynchronous Page Read Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read. See Figure 11: Asynchronous Page Read AC waveforms, and Table 20: Asynchronous Page Read AC characteristics, for details on when the outputs become valid. 3.1.4 Asynchronous Bus Write Asynchronous Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and Output Enable High, VIH, or Output Disable Low, VIL. The Address inputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 12: Asynchronous Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements. 3.1.5 Asynchronous Latch Controlled Bus Write Asynchronous Latch Controlled Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is Don't care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on the Address inputs and pulsing Latch Enable Low, VIL. The Address inputs are latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 13: Asynchronous Latch controlled Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements. 3.1.6 Output Disable The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL. 25/87 Bus operations M58BW16F, M58BW32F 3.1.7 Standby When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level (IDD1) and the Data inputs/outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1' (see Table 18: DC characteristics). 3.1.8 Reset/Power-down The memory is in Reset/Power-down mode when Reset/Power-down, RP, is at VIL. The power consumption is reduced to the standby level (IDD1) and the outputs are high impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. In this mode the device is write protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. Table 6. Asynchronous Bus operations(1) Step E VIL Address Latch Read VIL VIL VIL VIL Address Latch Write VIL VIL VIL VIL VIH X G VIL VIH VIL VIL VIH VIH VIH VIH VIL X X GD VIH VIH VIH VIH X X X VIH VIL X X W VIH VIL VIH VIH VIL VIH VIL VIH VIH X X RP VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL L VIL VIL VIH X VIL VIL VIH X X X X A0-Amax Address Address X Address Address Address X X X X X DQ0-DQ31 Data output High Z Data output Data output Data input High Z Data input High Z High Z High Z High Z Bus operation Asynchronous Bus Read(2) Asynchronous Latch Controlled Bus Read Asynchronous Page Read Asynchronous Bus Write Asynchronous Latch Controlled Bus Write Output Enable, G Output Disable, GD Standby Reset/Power-down 1. X = Don't care. 2. Data, Manufacturer code, Device code, Burst Configuration Register, Standby Status and Block Protection Configuration Register are read using the Asynchronous Bus Read command. 26/87 M58BW16F, M58BW32F Bus operations 3.2 Synchronous Bus operations For Synchronous Bus Operations refer to Table 7 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL. 3.2.1 Synchronous Burst Read Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The valid edge of the Clock signal is the rising edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active clock signal since the switching of the output buffer databus is synchronized to the rising edge of the clock. In the absence of clock, no data is output. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figure 4 for examples of Synchronous Burst operations. A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst Address counter on the valid Burst Clock K edge or on the rising edge of Latch Enable, whichever occurs first. After an initial memory latency time, the memory outputs data each clock cycle. The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B, is Low. Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the rising clock edge. Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid. If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock K rising edge. The Synchronous Burst Read timing diagrams and AC characteristics are described in the AC and DC parameters section. See Figures 14, 17, 18 and 19, and Table 22. 27/87 Bus operations M58BW16F, M58BW32F 3.2.2 Synchronous Burst Read Suspend During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the Burst counter and the Output Enable going High, VIH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low. Table 7. Synchronous Burst Read Bus operations(1) Step Address Latch Read Read Suspend Synchronous Burst Read(2) Read Resume Burst Address Advance Read Abort, E Read Abort, RP 1. X = Don't care, VIL or VIH. 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. R = Rising edge. Bus operation E VIL VIL VIL VIL VIL VIH X G VIH VIL VIH VIL VIH X X GD X VIH X VIH X X X RP VIH VIH VIH VIH VIH VIH VIL K R(3) R(3) X R(3) R(3) X X L VIL VIH VIH VIH VIH X X B X VIL VIH VIL VIL X X A0-Amax DQ0-DQ31 Address input Data output High Z Data output High Z High Z High Z 3.3 Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Powerdown mode. The Burst Configuration Register bits are described in Table 8. They specify the selection of the Burst length, Burst type, Burst X and Y latencies and the Read operation. Refer to Figure 4 for examples of Synchronous Burst configurations. 3.3.1 Read Select bit (M15) The Read Select bit, M15, is used to switch between Asynchronous and Synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select bit is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to'1' for asynchronous accesses. 3.3.2 Standby Disable bit (M14) The Standby Disable bit, M14, is used to disable the Standby mode. When the Standby bit is `1', the device will not enter Standby mode when Chip Enable goes High, VIH. 28/87 M58BW16F, M58BW32F Bus operations 3.3.3 X-Latency bits (M13-M11) The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock edges between the address being latched and the edge where the first data become available. For correct operation the X-Latency bits can only assume the values in Table 8: Burst Configuration Register. 3.3.4 Y-Latency bit (M9) The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the XLatency value and the setting in M9. When the Y-Latency is 1 the data changes each clock cycle. 3.3.5 Valid Data Ready bit (M8) The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the rising clock edge when invalid data is output on the bus. 3.3.6 Wrap Burst bit (M3) Burst Read can be confined inside the 4 double-word boundary (wrap) or overcome the boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The wrap mode is not available (M3 is always `1'). 3.3.7 Burst Length bit (M2-M0) The Burst Length bits set the maximum number of double-words that can be output during a Synchronous Burst Read operation. Burst lengths of 4 or 8 are available. Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts. If a Burst Read operation (no wrap) has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 double word boundary, the 8-double-word burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to a 4 double word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M7 to M4 are reserved for future use. 29/87 Bus operations Table 8. Bit M15 M58BW16F, M58BW32F Burst Configuration Register Description 0 Read Select 1 0 M14 Standby Disable 1 000 001 010 Standby mode disabled Reserved (default value) 3, 3-1-1-1, 3-2-2-2 4, 4-1-1-1, 4-2-2-2 5, 5-1-1-1, 5-2-2-2 6, 6-1-1-1, 6-2-2-2 7, 7-1-1-1, 7-2-2-2 8, 8-1-1-1, 8-2-2-2 Reserved Reserved (default value) Reserved One Burst Clock cycle (default value) Two Burst Clock cycle R valid Low during valid Burst Clock edge (default value) R valid Low 1 data cycle before valid Burst Clock edge Reserved (default value) Reserved Falling Burst Clock edge (default value) Rising Burst Clock edge Reserved (default value) Reserved Reserved Reserved Wrap (default value) No Wrap Asynchronous Read (default at power-on) Standby mode enabled (default at power-up) Value Description Synchronous Burst Read M13-M11 X-Latency(1) 011 100 101 110 111 0 M10 1 M9 Y-Latency(2) 0 1 0 M8 Valid Data Ready 1 0 M7 1 M6(3) 0 1 00 01 M5-M4 10 11 0 M3 Wrapping 1 30/87 M58BW16F, M58BW32F Table 8. Bit Bus operations Burst Configuration Register (continued) Description Value 000 001 010 011 Description Reserved (default value) 4 double-words 8 double-words Reserved Reserved Reserved Reserved Continuous M2-M0 Burst Length 100 101 110 111 1. X latencies can be calculated as: (tAVQV - tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. X is an integer number from 4 to 8, tK is the clock period and tSYSTEM MARGIN is the time margin required for the calculation. 2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK. 3. The M6 bit is Don't care in the M58BW32F and the device has the Rising Burst Clock edge set. To maintain the compatibility this could be modified and read. 31/87 Bus operations Table 9. Burst type definition x 4 sequential 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 4-5-6-7 5-6-7-8 6-7-8-9 7-8-9-10 8-9-10-11 M58BW16F, M58BW32F Start address 0 1 2 3 4 5 6 7 8 x 8 sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 8-9-10-11-12-13-14-15 Figure 4. Example burst configuration X-1-1-1 0 1 2 3 4 5 6 7 8 9 K ADD VALID L DQ 3-1-1-1 VALID VALID VALID VALID VALID VALID VALID DQ 4-1-1-1 VALID VALID VALID VALID VALID VALID DQ 5-1-1-1 VALID VALID VALID VALID VALID DQ DQ DQ 6-1-1-1 VALID VALID VALID VALID 7-1-1-1 VALID VALID VALID VALID VALID 8-1-1-1 AI03841b 32/87 M58BW16F, M58BW32F Command interface 4 Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. The commands are summarized in Table 10: Commands. Refer to Table 10 in conjunction with the text descriptions below. 4.1 Read Memory Array command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent Read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array. 4.2 Read Electronic Signature command The Read Electronic Signature command is used to read the Manufacturer code, the Device code, the Block Protection Configuration Register and the Burst Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, subsequent Bus Read operations, depending on the address specified, read the Manufacturer code, the Device code, the Block Protection Configuration or the Burst Configuration Register until another command is issued; see Table 11: Read electronic signature. 4.3 Read Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the common Flash interface memory area. 33/87 Command interface M58BW16F, M58BW32F 4.4 Read Status Register command The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ0-DQ7) when Chip Enable E and Output Enable G are at VIL and Output Disable is at VIH. An interactive update of the Status Register bits is possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase operation, by de-activating the device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable at VIH. The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation. During a Block Erase or Program command, DQ7 indicates the Program/Erase controller status. It is valid until the operation is completed or suspended. See the section on the Status Register and Table 13 for details on the definitions of the Status Register bits. 4.5 Clear Status Register command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. 4.6 Block Erase command The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block Erase command and latches the block address in the Program/Erase controller and starts the Program/Erase controller. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with bits 4 and 5 set to '1'. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to `1' and the command must be reissued. Typical Erase times are given in Table 12. See Appendix A, Figure 28: Block Erase flowchart and pseudocode, for a suggested flowchart on using the Block Erase command. 34/87 M58BW16F, M58BW32F Command interface 4.7 Erase All Main Blocks command The Erase All Main Blocks command is used to erase all 63 main blocks, without affecting the parameter blocks. Issuing the Erase All Main Blocks command sets every bit in each main block to '1'. All data previously stored in the main blocks are lost. Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first cycle sets up the command, the second cycle confirms the command and starts the Program/Erase controller. If the Confirm command is not given the sequence is aborted, and Status Register bits 4 and 5 are set to '1'. If the address given in the second cycle is located in a protected block, the Erase All Main Blocks operation aborts. The data remains unchanged in all blocks and the Status Register outputs the error. Once the Erase All Main Blocks command has been issued, subsequent Bus Read operations output the Status Register. See the Status Register section for details. During an Erase All Main Blocks operation, only the Read Status Register command is accepted by the memory; any other command are ignored. Erase All Main Blocks, once started, cannot be suspended. If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'. 4.8 Program command The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed and starts the Program/Erase controller. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. The Program command is also used to program the OTP block. Refer to Table 10: Commands, for details of the address. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If Reset/Power-down, RP, falls to VIL during programming the operation will be aborted. If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to `1' and the command must be reissued. See Appendix A, Figure 26: Program flowchart and pseudocode, for a suggested flowchart on using the Program command. 35/87 Command interface M58BW16F, M58BW32F 4.9 Write to Buffer and Program command The Write to Buffer and Program command makes use of the device's double word (32 bit) Write Buffer to speed up programming. Up to eight double words can be loaded into the Write Buffer and programmed into the memory. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program command. Any Bus Read operations will start to output the Status Register after the 1st cycle. Use one Bus Write operation to write the selected memory block address (any address in the block where the values will be programmed can be used) along with the value N on the Data inputs/outputs, where N+1 is the number of words to be programmed. The maximum value of N+1 is 8 words. Use N+1 Bus Write operations to load the address and data for each word into the write buffer. The address must be between Start address and Start address plus N, where Start address is the first word address. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. 2. 3. 4. If any address is outside the block boundaries or if the correct sequence is not followed, Status Register bits 4 and 5 are set to `1' and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'. The Status Register should be cleared before re-issuing the command. 36/87 M58BW16F, M58BW32F Command interface 4.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a Program or Erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller has paused; no other commands will be accepted until the Program/Erase controller has paused. After the Program/Erase controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase controller pausing see Table 12. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the command interface. Additionally, if the suspended operation was Erase then the Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration Register and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. Erase operations can be suspended in a systematic and periodical way, however, in order to ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative to wait a minimum time between successive Erase Resume and Erase Suspend commands. This time, called the minimum effective erase time, is given in Table 12 on page 40. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command. 4.11 Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command. 37/87 Command interface M58BW16F, M58BW32F 4.12 Set Burst Configuration Register command The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous Read mode. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command. The second cycle writes the address where the new Burst Configuration Register content is to be written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored. 4.13 Set Block Protection Configuration Register command The Set Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `protected', for a specific block. Protected blocks are fully protected from program or erase when WP pin is Low, VIL. The status of a protected block can be changed to `unprotected' by using the Clear Block Protection Configuration Register command. At power-up, all block are configured as `protected'. Two bus operations are required to issue a Set Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to protect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To protect multiple blocks, the Set Block Protection Configuration Register command must be repeated for each block. Any attempt to re-protect a block already protected does not change its status. 4.14 Clear Block Protection Configuration Register command The Clear Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `unprotected', for a specific block thus allowing program/erase operations to this block, regardless of the WP pin status. Two bus operations are required to issue a Clear Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to unprotect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be repeated for each block. Any attempt to unprotect a block already unprotected does not affect its status. 38/87 M58BW16F, M58BW32F Table 10. Commands(1) Bus operations Cycles Command 1st cycle Op. Addr. Data Read Memory Array 2 Write X X X X X Op. 2nd cycle Addr. RA IDA Data RD IDD 3rd cycle Command interface 4th cycle Op. Addr. Data Op. Addr. Data FFh Read 90h Read 70h 98h Read 50h 20h Write 80h Write 40h Write 10h 40h Write E8h Write B0h D0h Read Electronic Signature(2) 2 Write Read Status Register Read Query Clear Status Register Block Erase Erase All Main Blocks any block Program OTP block 2 1 Write 2 Write 1 2 2 2 Write RA RD Write 55h Write 55h Write AAh Write AAh BA AAh PA PA BA D0h D0h PD PD N Write PA PD Write X D0h Write to Buffer and Program N+4 Write AAh Program/Erase Suspend Program/Erase Resume Set Burst Configuration Register Set Block Protection Configuration Register Clear Block Protection Configuration Register 1 1 Write Write X X X X X S3 Write 2 2 Write Write 60h Write BCRh 60h Write 60h Write BA BA 03h 01h D0h Read RA RD 1. X Don't care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, N+1 number of Words to program, BA Block address. 2. The Manufacturer code, the Device code, the Burst Configuration Register, and the Block Protection Configuration Register of each block are read using the Read Electronic Signature command. 39/87 Command interface Table 11. Read electronic signature Device All M58BW16FT M58BW16FB Device M58BW32FT M58BW32FB Burst Configuration Register Block Protection Configuration Register 1. BCR = Burst Configuration Register. 2. SBA is the start address of each block. M58BW16F, M58BW32F Code Manufacturer Amax-A0 00000h 00001h 00001h 00001h 00001h 00005h SBA+02h(2) DQ31-DQ0 00000020h 0000883Ah 00008839h 00008838h 00008837h BCR(1) 00000000h (Unprotected) 00000001h (Protected) All Table 12. Program, Erase times and endurance cycles(1) M58BW16F Parameters Min Typ 15 15 1 0.8 0.6 45 Max 20 35 2 1.6 1.2 60 10 30 (2) M58BW32F Unit Min Typ 15 15 1 0.8 0.6 30 Max 20 35 2 1.6 1.2 50 10 30 40 100,000 s s s s s s s s s cycles Full Chip Program Double Word Program 512 Kbit Block Erase 128 Kbit Block Erase 64 Kbit Block Erase Erase all main blocks Program Suspend Latency time Erase Suspend Latency time Minimum effective erase time 40 100,000 Program/Erase cycles (per block) 1. TA = -40 to 125 C, VDD = 2.7 V to 3.6 V, VDDQ = 2.6 V to VDD. 2. The minimum effective erase time is defined as the minimum time required between the last Erase Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase controller to be able to execute its algorithm. 40/87 M58BW16F, M58BW32F Status Register 5 Status Register The Status Register provides information on the current or previous Program, Erase or Block Protect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands. The Status Register can be read from any address. The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by de-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device. The Status Register bits are summarized in Table 13: Status Register bits. Refer to Table 13 in conjunction with the following text descriptions. 5.1 Program/Erase Controller Status (bit 7) The Program/Erase Controller Status bit indicates whether the Program/Erase controller is active or inactive. When the Program/Erase Controller Status bit is set to `0', the Program/Erase controller is active; when bit 7 is set to `1', the Program/Erase controller is inactive. The Program/Erase Controller Status is set to `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is set to `1'. During Program and Erase operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase controller completes the operation and the bit is set to `1'. After the Program/Erase controller completes its operation the Erase Status (bit 5), Program Status (bit 4) bits should be tested for errors. 5.2 Erase Suspend Status (bit 6) The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is set to `0', the Program/Erase controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'. 41/87 Status Register M58BW16F, M58BW32F 5.3 Erase Status (bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When the Erase Status bit is set to `0', the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to `1', the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to `1', the Erase Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.4 Program/Write to Buffer and Program Status (bit 4) The Program/Write to Buffer and Program Status bit is used to identify a Program failure or a Write to Buffer and Program failure. Bit 4 should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When bit 4 is set to `0' the memory has successfully verified that the device has programmed correctly. When bit 4 is set to `1' the device has failed to verify that the data has been programmed correctly. Once set to `1', the Program Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.5 PEN Status (bit 3) The PEN Status bit can be used to identify if a Program or Erase operation has been attempted when PEN is Low, VIL. When bit 3 is set to `0' no Program or Erase operations have been attempted with PEN Low, VIL, since the last Clear Status Register command, or hardware reset. When bit 3 is set to `1' a Program or Erase operation has been attempted with PEN Low, VIL. Once set to `1', bit 3 can only be reset by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 42/87 M58BW16F, M58BW32F Status Register 5.6 Program Suspend Status (bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is set to `0', the Program/Erase controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. 5.7 Block Protection Status (bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is set to `0', no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is set to `1', a Program or Erase operation has been attempted on a protected block. Once set to `1', the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.8 Bit 0 Reserved bit (set to `1'). 43/87 Status Register Table 13. Bit 7 M58BW16F, M58BW32F Status Register bits Name Program/Erase Controller Status '0' '1' 6 Erase Suspend Status '0' '1' 5 Erase Status '0' '1' 4 Program Status, '0' `0' 3 PEN Status bit `1' '1' 2 Program Suspend Status '0' Erase/Program in a protected block Reserved '1' '0' 0 '1' In progress or completed Program/erase on protected block, abort No operations to protected blocks Reserved Program or erase attempted Suspended Program success No program or erase attempted Erase success Program error In progress or completed Erase error Busy Suspended Logic level '1' Ready Definition 1 44/87 M58BW16F, M58BW32F Maximum rating 6 Maximum rating Stressing the device above the ratings listed in Table 14: Absolute maximum ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 14. Absolute maximum ratings Value Symbol TBIAS TSTG VIO Parameter Min Temperature under bias Storage temperature Input or output voltage -40 -55 -0.6 -0.6 Max 125 155 VDDQ + 0.6 VDDQIN + 0.6 4.2 C C V V Unit VDD, VDDQ, VDDQIN Supply voltage Table 15. Data retention External temperature Unit 25 C V V V 20 - - 125 C 7 25 15 Years Years Years Unit Power supply VDD 0 2.5 2.7 45/87 DC and AC parameters M58BW16F, M58BW32F 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 16: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 16. Operating and AC measurement conditions M58BW16F, M58BW32F Parameter Min Supply voltage (VDD) Input/output supply voltage (VDDQ) Ambient temperature (TA) Load capacitance (CL) Clock rise and fall times Input rise and fall times Input pulses voltages Input and output timing ref. voltages Grade 3 2.7 2.4 -40 30 3 3 0 to VDDQ VDDQ/2 45 ns Max 3.6 3.6 125 Min 2.5 2.4 -40 30 3 3 0 to VDDQ VDDQ/2 55 ns Max 3.3 3.6 125 V V C pF ns ns V V Units Figure 5. AC measurement input/output waveform VDDQ VDDQIN VDDQ/2 VDDQIN/2 0V AI04153 1. VDD = VDDQ. Figure 6. AC measurement load circuit DEVICE UNDER TEST CL OUT CL includes JIG capacitance AI04154b 46/87 M58BW16F, M58BW32F Table 17. Symbol CIN COUT DC and AC parameters Device capacitance(1)(2) Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V Typ 6 8 Max 8 12 Unit pF pF 1. TA = 25 C, f = 1 MHz. 2. Sampled only, not 100% tested. Table 18. Symbol ILI ILO IDD DC characteristics Parameter Input Leakage current Output Leakage current Supply current (Random Read) Test condition 0 VVIN VDDQIN 0 V VOUT VDDQ E = VIL, G = VIH, fadd = 6 MHz Min Typ Max 1 5 25 20 E = VIL, G = VIH, fclock = 75 MHz E = RP = VDD 0.2 V Program, Erase in progress E = VIH 5 -0.5 0.8VDDQIN 0.8VDDQIN IOL = 100 A IOH = -100 A VDDQ -0.1 2.2 50 150 30 150 10 0.2VDDQIN VDDQ + 0.3 3.6 0.1 Unit A A mA mA mA A mA A mA V V V V V V IDDP-UP(1) Supply current (power-up) IDDB IDD1(2) IDD2 IDD3 IDD4 VIL VIH VIH VOL VOH VLKO Supply current (Burst Read) Supply current (Standby) Supply current (Program or Erase) Supply current (Erase/Program Suspend) Supply current (Standby Disable) Input Low voltage Input High voltage (for DQ lines) Input High voltage (for input only lines) Output Low voltage Output High voltage CMOS VDD supply voltage (Erase and Program lockout) 1. IDDP-UP is the current needed from the device until RP goes to its logic high level when the power supply is stable (tVDHPH). See Figure 22and Figure 23. 2. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1'. 47/87 DC and AC parameters Figure 7. Asynchronous Bus Read AC waveforms tAVAV A0-A19 tAVQV L tELQX tELQV E tGLQX tGLQV G VALID tEHLX M58BW16F, M58BW32F tAXQX tEHQX tEHQZ GD tGHQX tGHQZ DQ0-DQ31 OUTPUT See also Page Read AI08921b Figure 8. A0-A19 Asynchronous Latch Controlled Bus Read AC waveforms VALID tLHAX L tLHLL tLLLH tEHLX E tGLQX tGLQV G tLLQV tLLQX DQ0-DQ31 OUTPUT See also Page Read AI08922b tEHQX tEHQZ tGHQX GHQZ 48/87 M58BW16F, M58BW32F Figure 9. A0-A19 DC and AC parameters Asynchronous Chip Enable Controlled Bus Read AC waveforms VALID tLHAX L tEHLX E tGLQX tGLQV G tELQX tELQV DQ0-DQ31 OUTPUT See also Page Read AI13434 tEHQX tEHQZ tGHQX GHQZ Figure 10. Asynchronous Address Controlled Bus Read AC waveforms A0-A19 VALID tLHAX L E tGLQX tGLQV G tAVQV DQ0-DQ31 tEHLX tEHQX tEHQZ tGHQX GHQZ OUTPUT See also Page Read AI13435 49/87 DC and AC parameters Table 19. Symbol M58BW16F, M58BW32F Asynchronous Bus Read AC characteristics M58BWxxF Parameter Test condition 45 55 55 55 0 0 0 20 55 0 15 15 0 5 10 10 55 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tAVAV tAVQV tAXQX tEHLX tEHQX tEHQZ Address Valid to Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Latch Enable Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z E = VIL, G = VIL E = VIL, G = VIL L = VIL, G = VIL Min Max Min Min 45 45 0 0 0 20 45 0 15 15 0 5 10 10 45 0 0 G = VIL G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL Min Max Max Min Max Max Min Min Min tELQV(1) Chip Enable Low to Output Valid tGHQX tGHQZ tGLQV tGLQX tLHAX tLHLL tLLLH tLLQV tLLQX tELQX Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable High to Latch Enable Low Latch Enable Low to Latch Enable High Latch Enable Low to Output Valid Chip Enable Low to Output Valid Latch Enable Low to Output Transition Chip Enable Low to Output Transition E = VIL E = VIL, G = VIL E = VIL, G = VIL L = VIL, G = VIL Min Max Min Min 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV. 50/87 M58BW16F, M58BW32F Figure 11. Asynchronous Page Read AC waveforms DC and AC parameters A0-A1 A0 and/or A1 tAVQV1 tAXQX DQ0-DQ31 OUTPUT OUTPUT + 1 AI03646 Table 20. Symbol tAVQV1 tAXQX Asynchronous Page Read AC characteristics(1) M58BWxxF Parameter Address Valid to Output Valid Address Transition to Output Transition Test condition 45 E = VIL, G = VIL E = VIL, G = VIL Max Min 25 0 55 25 0 ns ns Unit 1. For other timings see Table 19: Asynchronous Bus Read AC characteristics. 51/87 52/87 VALID tAVAV tAVWH tWHAX VALID VALID tWHEH tELWL tWLWH tWHGL tWHWL tDVWH INPUT tWHDX INPUT tWHQV VALID SR DC and AC parameters A0-A19 E=L tAVLL G W Figure 12. Asynchronous Write AC waveforms DQ0-DQ31 tVPHWH tQVVPL PEN tPHWH RP = VHH tQVPL RP = VDD RP Write Cycle Write Cycle Read Status Register AI13223b M58BW16F, M58BW32F A0-A19 VALID tAVAV tAVLH tLHAX VALID VALID M58BW16F, M58BW32F L tWHAX tLLWH tELLL tLLLH tAVLL E tAVWH G tELWL tWLWH tWHWL tWHEH tWHGL W tDVWH INPUT tWHDX tVPHWH INPUT tWHQV VALID SR tQVVPL Figure 13. Asynchronous Latch controlled Write AC waveforms DQ0-DQ31 PEN tQVPL RP = VHH RP = VDD RP Write Cycle Write Cycle Read Status Register AI13222b DC and AC parameters 53/87 DC and AC parameters Table 21. Symbol tAVAV tAVLH tAVLL tAVWH tDVWH tELLL tELWL tLHAX tLLLH tLLWH tQVVPL tVPHWH tWHAX tWHDX tWHEH tWHGL tWHQV tWHWL tWLWH tQVPL M58BW16F, M58BW32F Asynchronous Write and Latch controlled Write AC characteristics M58BWxxF Parameter Address Valid to Address Valid Address Valid to Latch Enable High Address Valid to Latch Enable Low Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Latch Enable Low Chip Enable Low to Write Enable Low Latch Enable High to Address Transition Latch Enable Low to Latch Enable High latch Enable Low to Write Enable High Output Valid to PEN Low PEN High to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Output Valid Write Enable High to Write Enable Low Write Enable Low to Write Enable High Output Valid to Reset/Power-down Low E = VIL E = VIL E = VIL E = VIL E = VIL E = VIL Test condition 45 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 45 8 0 25 25 0 0 5 10 25 0 0 0 0 0 150 165 20 25 0 55 55 8 0 30 30 0 0 5 10 30 0 0 0 0 0 150 165 20 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 54/87 M58BW16F, M58BW32F 0 1 n n+1 n+2 K tKHAX VALID tLLKH tKHLH tKHLL A0-A19 L tAVLL tELLL tEHQX tEHQZ E tGLQV tGHQX tGHQZ G tKHQV OUTPUT DQ0-DQ31 Setup Note: n depends on Burst X-Latency. AI08925c Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from 'n' clock rising edge) DC and AC parameters 55/87 56/87 0 1 n n+1 n+2 tBLKH tKHAX VALID tELKH tKHLH tEHQX tEHQZ tGLQV tGHQX tGHQZ tKHQV OUTPUT Setup AI13284 DC and AC parameters K B tKHEL A0-A19 L E G DQ0-DQ31 Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from 'n' clock rising edge) M58BW16F, M58BW32F Note: n depends on Burst X-Latency. M58BW16F, M58BW32F DC and AC parameters Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid from 'n' clock rising edge) tGHQX tGHQZ tEHQX tEHQZ AI13285 n+1 n+2 tBLKH n tKHAX tGLQV tKHQV OUTPUT 1 VALID tKHLH Setup DQ0-DQ31 A0-A19 E G L Note: n depends on Burst X-Latency. 0 K B tAVKH 57/87 DC and AC parameters M58BW16F, M58BW32F Figure 17. Synchronous Burst Read (data valid from 'n' clock rising edge) n K tKHQV n+1 n+2 n+3 n+4 n+5 DQ0-DQ31 Q0 Q1 tKHQX Q2 Q3 Q4 Q5 SETUP Burst Read Q0 to Q3 Note: n depends on Burst X-Latency AI04408c 1. For set up signals and timings see Synchronous Burst Read. Figure 18. Synchronous Burst Read - valid data ready output K Output (1) V V V tRLKH V V R (2) AI03649b 1. Valid Data Ready = Valid Low during valid clock edge. 2. V= Valid output. 3. The internal timing of R follows DQ. 58/87 M58BW16F, M58BW32F Figure 19. Synchronous Burst Read - Burst Address Advance DC and AC parameters K A0-A19 VALID L DQ0-DQ31 tGLQV G tBLKH B Q0 Q1 Q2 tBHKH AI03650 Figure 20. Clock input AC waveform tKHKL K tKLKH ai13286 59/87 DC and AC parameters Table 22. Symbol M58BW16F, M58BW32F Synchronous Burst Read AC characteristics(1)(2) M58BWxxF Parameter Test condition 45 X-Latency = 3 Max Max Max Min Min Min Min E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH L = VIL X-Latency = 3 Min Min Min Min Max Min Min Min Min Min Min Min Min Min Max 40 56 75 12 6 6 6 8 8 12 6 15 5 0 0 0 2 12 6 6 6 8 55 33 40 56 13 7 6 6 8 8 13 7 15 5 0 0 0 2 13 5 7 6 8 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit f Clock frequency X-Latency = 4 X-Latency = 5 or 6 E = VIL, L = VIL X-Latency = 3 tAVKH Address Valid to Valid Clock Edge E = VIL, L = VIL X-Latency = 4, 5 or 6 Clock High time Clock Low time Burst Address Advance High to Valid Clock Edge Burst Address Advance Low to Valid Clock Edge tKHKL tKLKH tBHKH tBLKH tELKH Chip Enable Low to Valid Clock Edge L = VIL X-Latency = 4, 5 or 6 Output Enable Low to Output Valid Valid Clock Edge to Address Transition Valid Clock Edge to Chip Enable Low Valid Clock Edge to Latch Enable Low Valid Clock Edge to Latch Enable High Valid Clock Edge to Output Transition E = VIL, L = VIH E = VIL L = VIL E = VIL E = VIL E = VIL, G = VIL, L = VIH E = VIL X-Latency = 3 E = VIL X-Latency = 4, 5 or 6 M58BW16F M58BW32F tGLQV tKHAX tKHEL tKHLL tKHLH tKHQX tLLKH Latch Enable Low to Valid Clock Edge tRLKH tKHQV Valid Data Ready Low to Valid Clock Edge Valid Clock Edge to Output Valid E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH 1. Data output should be read on the valid clock edge. 2. For other timings see Table 19: Asynchronous Bus Read AC characteristics. 60/87 M58BW16F, M58BW32F Figure 21. Power supply slope specification Voltage DC and AC parameters VDHH VDH tVDH Time AI14230b 1. Please refer to the application note AN2601. Table 23. Symbol VDH VDHH tVDH Power supply AC and DC characteristics Description Minimum value of power supply (VDD)(1) Maximum value of power supply (VDD) Time required from power supply to reach the VDH value 300 Min 0.9VDD 3.6 50000 Max Unit V V s 1. This threshold is 90% of the minimum value allowed to VDD. 61/87 DC and AC parameters M58BW16F, M58BW32F Figure 22. Reset, Power-down and Power-up AC waveforms - Control pins Low W, E, G, L tPHWL tPHEL tPHGL tPHLL Hi-Z Hi-Z tPHRH tPLRZ tPHRH R RP tVDHPH VDD, VDDQ Power-up Reset AI14239 tPLPH Figure 23. Reset, Power-down and Power-up AC waveforms - Control pins toggling tWLRH tGLRH tELRH tLLRH tPLRZ Hi-Z tPHRH tPHRH RP tVDHPH VDD, VDDQ Power-up Reset AI14240 W, E, G, L tPHWL tPHEL tPHGL tPHLL Hi-Z R tPLPH 62/87 M58BW16F, M58BW32F Table 24. Symbol tPHEL tPHLL tPHQV(1) tPHWL tPHGL tPLPH tPHRH(1) tVDHPH tPLRZ tWLRH tGLRH tELRH tLLRH DC and AC parameters Reset, Power-down and Power-up AC characteristics Parameter Reset/Power-down High to Chip Enable Low Reset/Power-down High to Latch Enable Low Reset/Power-down High to Output Valid Reset/Power-down High to Write Enable Low Reset/Power-down High to Output Enable Low Reset/Power-down Low to Reset/Power-down High Reset/Power-down High to Valid Data Ready High Supply voltages High to Reset/Power-down High Reset/Power-down Low to Data Ready High Impedance Write Enable Low to Data Ready High Impedance Output Enable Low to Data Ready High Impedance Chip Enable Low to Data Ready High Impedance Latch Enable Low to Data Ready High Impedance 50 80 80 80 80 80 50 50 100 95 Min 50 50 95 Max Unit ns ns ns ns ns ns ns s ns ns ns ns ns 1. This time is tPHEL + tAVQV or tPHEL + tELQV. 63/87 Package mechanical M58BW16F, M58BW32F 8 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 24. LBGA80 10 x 12 mm - 8 x 10 ball array, 1 mm pitch, bottom view package outline D FD FE SD D1 SE E E1 BALL "A1" ddd e e A A1 b A2 JE_ME 1. Drawing is not to scale. 64/87 M58BW16F, M58BW32F Table 25. Package mechanical LBGA80 10 x 12 mm - 8 x 10 active ball array, 1 mm pitch, package mechanical data millimeters inches Max 1.60 0.40 1.05 0.60 10.00 7.00 - - - - 0.15 12.00 9.00 1.00 1.50 1.50 - - - - - 0.50 0.50 - - - - - 0.472 0.354 0.039 0.059 0.059 - - - - - 0.020 0.020 0.024 0.394 0.276 - - - - 0.006 - - - - - 0.016 0.041 Typ Min Max 0.063 Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE Min 65/87 Package mechanical M58BW16F, M58BW32F Figure 25. PQFP80 - 80 lead plastic quad flat pack, package outline Ne A2 N 1 e Nd D2 D1 D b E2 E1 E L1 A CP c QFP-B A1 L 1. Drawing is not to scale. Table 26. Symbol PQFP80 - 80 lead plastic quad flat pack, package mechanical data millimeters Typ Min Max 3.40 0.25 2.80 2.55 0.30 3.05 0.45 0.10 0.13 23.20 20.00 18.40 0.80 17.20 14.00 12.00 0.80 1.60 22.95 19.90 - - 16.95 13.90 - 0.65 - 0 80 24 16 0.23 23.45 20.10 - - 17.45 14.10 - 0.95 - 7 0.913 0.787 0.724 0.031 0.677 0.551 0.472 0.031 0.063 0.005 0.903 0.783 - - 0.667 0.547 - 0.026 - 0 80 24 16 0.110 0.010 0.100 0.012 0.120 0.018 0.004 0.009 0.923 0.791 - - 0.687 0.555 - 0.037 - 7 Typ inches Min Max 0.134 A A1 A2 b CP c D D1 D2 e E E1 E2 L L1 N Nd Ne 66/87 M58BW16F, M58BW32F Ordering information 9 Ordering information Table 27. Example: Device type M58 Architecture B = Burst mode Operating voltage W = [2.7 V to 3.6 V] VDD range for 45 ns speed class [2.5 V to 3.3 V] VDD range for 55 ns speed class [2.4 V to VDD] VDDQ range for 45 ns and 55 ns speed classes Device function 32F = 32 Mbit (x 32), boot block, burst, 0.11 m technology 16F = 16 Mbit (x 32), boot block, burst, 0.11 m technology Array matrix T = Top boot B = Bottom boot Speed 4 = 45 ns 5 = 55 ns Package T = PQFP80 ZA = LBGA80, 1.0 mm pitch Device grade 3 = Automotive grade certified(1), -40 to 125 C Option Blank = Standard packing T = Tape & reel packing F = ECOPACK(R) package, tape & reel 24 mm packing 1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. Ordering information scheme M58BW32F T4T3 T Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 67/87 Flowcharts M58BW16F, M58BW32F Appendix A Flowcharts Figure 26. Program flowchart and pseudocode Start Write 40h Write Address & Data Program command: - write 40h, Address AAh - write Address & Data (memory enters read status state after the Program command) Read Status Register do: - read status register (E or G must be toggled) NO b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End while b7 = 1 NO PEN Invalid Error (1) If b3 = 1, PEN invalid error: - error handler NO Program Error (1) If b4 = 1, Program error: - error handler NO Program to Protect Block Error If b1 = 1, Program to Protected Block Error: - error handler AI03850e 1. If an error is found, the Status Register must be cleared before further P/E operations. 68/87 M58BW16F, M58BW32F Figure 27. Program Suspend & Resume flowchart and pseudocode Start Flowcharts Write B0h Write 70h Program/Erase Suspend command: - write B0h - write 70h do: - read status register Read Status Register b7 = 1 YES b2 = 1 YES Write FFh NO while b7 = 1 NO Program Complete If b2 = 0, Program completed Read Memory Array command: - write FFh - one or more data reads from other blocks Read data from another block Write D0h Write FFh Program Continues Read Data Program Erase Resume command: - write D0h to resume programming - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued). AI00612b 69/87 Flowcharts Figure 28. Block Erase flowchart and pseudocode Start M58BW16F, M58BW32F Write 20h Write Block Address & D0h Erase command: - write 20h, Address 55h - write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) Read Status Register NO Suspend YES do: - read status register (E or G must be toggled) if Erase command given execute suspend erase loop while b7 = 1 b7 = 1 NO Suspend Loop YES b3 = 0 YES b4 and b5 =1 NO b5 = 0 YES b1 = 0 YES End AI08623d NO PEN Invalid Error (1) If b3 = 1, PEN invalid error: - error handler YES Command Sequence Error If b4, b5 = 1, Command Sequence error: - error handler NO Erase Error (1) If b5 = 1, Erase error: - error handler NO Erase to Protected Block Error If b1 = 1, Erase to Protected Block Error: - error handler 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 70/87 M58BW16F, M58BW32F Figure 29. Erase Suspend & Resume flowchart and pseudocode Flowcharts Erase cycle in progress Write B0h Program/Erase Suspend command Write 70h Read Status Register Do: - Read status register while b7 = 1 (b7 = Program/Erase status bit) b7 = 1 YES b6 = 1 YES Write FFh NO NO Erase Complete If b6 = 0, Erase is completed (b6 = Erase Suspend status bit) The device returns to Read mode as normal (as if the Program/Erase Suspend was not issued). Write FFh Read data from another block or Program Read Memory Array command: - Write FFh - One or more data reads from other blocks Read Data Write D0h Program/Erase Resume command: - Write D0h to resume the Erase operation Erase Continues AI00615c 71/87 Flowcharts Figure 30. Power-up sequence followed by Synchronous Burst Read M58BW16F, M58BW32F Power-up or Reset Asynchronous Read BCR bit 15 = '1' Write 60h command Set Burst Configuration Register command: - write 60h - write 03h and BCR on A15-A0 Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '0' BCR bit 14-bit 0 = '1' AI03834 72/87 M58BW16F, M58BW32F Figure 31. Command interface and Program/Erase controller flowchart (a) Flowcharts WAIT FOR COMMAND WRITE 90h YES READ ELEC. SIGNATURE NO READ ARRAY 98h YES READ CFI NO D 70h YES READ STATUS NO 20h YES ERASE SET-UP NO 40h YES NO ERASE COMMAND ERROR NO D0h YES A PROGRAM SET-UP 50h YES NO E C CLEAR STATUS D READ STATUS B AI03835 73/87 Flowcharts M58BW16F, M58BW32F Figure 32. Command interface and Program/Erase controller flowchart (b) E 48h YES TP PROGRAM SET_UP NO 78h YES NO F TP UNLOCK SET_UP 60h YES NO FFh G SET BCR SET_UP YES NO 03h YES NO D AI03836 74/87 M58BW16F, M58BW32F Figure 33. Command interface and Program/Erase controller flowchart (c) A Flowcharts B ERASE YES READY NO NO READ STATUS B0h YES ERASE SUSPEND YES READY NO NO ERASE SUSPENDED YES READ STATUS READ STATUS YES 70h NO YES PROGRAM SET_UP C YES READ STATUS 40h NO READ ARRAY NO D0h AI03837 75/87 Flowcharts M58BW16F, M58BW32F Figure 34. Command interface and Program/Erase controller flowchart (d) B C PROGRAM YES READY NO NO READ STATUS B0h YES PROGRAM SUSPEND YES READY NO NO PROGRAM SUSPENDED YES READ STATUS READ STATUS YES 70h NO READ ARRAY NO D0h YES READ STATUS AI03838 76/87 M58BW16F, M58BW32F Figure 35. Command interface and Program/Erase controller flowchart (e) Flowcharts B F TP PROGRAM YES READY NO READ STATUS B G TP UNLOCK YES READY NO READ STATUS AI03839 77/87 Common Flash interface (CFI) M58BW16F, M58BW32F Appendix B Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Table 28, Table 29, Table 30, Table 33 and Table 32 show the addresses used to retrieve the data. Table 28. Offset 00h 0020h 883A 8839 8838 8837 CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Alternate algorithm-specific extended query table Query structure overview Sub-section name Description Manufacturer code Numonyx M58BW16FT (top) M58BW16FB (bottom) M58BW32FT (top) M58BW32FB (bottom) 01h Device code 10h 1Bh 27h P(h)(1) A(h)(2) Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the primary algorithm (optional) Additional information specific to the alternate algorithm (optional) 1. Offset 15h defines P which points to the primary algorithm extended query address table. 2. Offset 19h defines A which points to the alternate algorithm extended query address table. 78/87 M58BW16F, M58BW32F Table 29. CFI - Query address and data output(1)(2) Data 51h 52h 59h 03h 00h 35h (M58BW16F) 39h (M58BW32F) 00h 00h 00h 00h "Q" "R" "Y" Common Flash interface (CFI) Address A0-Amax 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Instruction 51h; "Q" Query ASCII string 52h; "R" 59h; "Y" Primary vendor: Command set and control interface ID code Primary algorithm extended query address table: P(h) Alternate vendor: Command set and control interface ID code Alternate algorithm extended query address table 00h 1. The x 8 or byte address and the x 16 or word address mode are not available. 2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'. Table 30. Address A0-Amax 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h CFI - device voltage and timing specification Data 27h(1) 36h(1) xxxx xxxxh xxxx xxxxh 04h xxxx xxxxh 0Ah xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh VDD min VDD max Reserved Reserved 2n s typical for word, double word program Reserved 2n ms, typical time-out for Erase Block Reserved Reserved Reserved Reserved Reserved 1s 16 s Description Value 2.7 V 3.6 V 1. Bits are coded in binary code decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. 79/87 Common Flash interface (CFI) Table 31. M58BW16F device geometry definition Data 15h 03h 00h 00h 00h 02h 1Eh Description 2n number of bytes memory size Device interface sync./async. Organization sync./async. M58BW16F, M58BW32F Address A0-Amax 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Value 2 Mbytes x 32 Async. 32 bytes 2 31 blocks Maximum number of byte in multi-byte program = 2n Bit7-0 = number of Erase Block regions in device Number (n-1) of Erase Blocks of identical size; n=31 00h 00h 01h 07h Number (n-1) of Erase Blocks of identical size; n=8 00h 20h 00h Erase Block region information x 256 bytes per Erase 64 Kbits Block (8 Kbytes) 8 blocks Erase Block region information x 256 bytes per Erase 512 Kbits Block (64 Kbytes) 80/87 M58BW16F, M58BW32F Table 32. M58BW16F extended query information Address Amax-A0 35h 36h 37h 38h 39h Data (hex) 50 52 49 31h 31h P R Y Common Flash interface (CFI) Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h Description Query ASCII string - extended table Major revision number Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) bit1, Suspend Erase supported (1=yes) bit2, Suspend Program supported (1=yes) bit3, Lock/Unlock supported (0=no) bit4, Queue Erase supported (0=no) bit5, Instant individual block locking (0=no) bit6, Protection bits supported (0=no) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) Bit9, Reserved (P+5)h 3Ah 86h (P+6)h (P+7)h (P+8)h (P+9)h (P+A)h-(P+D)h (P+13)h-(P+40)h (P+41)h (P+42)h (P+43)h (P+44)h 3Bh 3Ch 3Dh 3Eh 3Fh-42h 48h-7Fh 80h 81h 82h 83h 01h 00h 00h 01h Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use Reserved Reserved xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh Unique device ID - 1 (16 bits) Unique device ID - 2 (16 bits) Unique device ID - 3 (16 bits) Unique device ID - 4 (16 bits) Synchronous Read supported 81/87 Common Flash interface (CFI) Table 33. M58BW32F device geometry definition Data 15h 03h 00h 00h 00h 02h 1Eh 00h 00h 01h 07h Description 2n number of bytes memory size Device interface sync./async. Organization sync./async. M58BW16F, M58BW32F Address A0-Amax 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h Value 4 Mbytes x 32 Async. 32 bytes 3 Maximum number of byte in multi-byte program = 2n Bit7-0 = number of Erase Block regions in device Number (n-1) of Erase Block regions of identical size; 62 blocks n = 31 Erase Block region information x 256 bytes per Erase 512 Kbits Block (64 Kbytes) Number (n-1) of Erase blocks of identical size; n = 8 8 blocks 00h 20h 00h 03h Number (n-1) of Erase Block of identical size; n = 8 00h 40h 00h Erase Block region information x 256 bytes per Erase 128 Kbits block (16 Kbytes) 8 blocks Erase Block region information x 256 bytes per Erase 64 Kbits Block (8 Kbytes) 82/87 M58BW16F, M58BW32F Table 34. M58BW32F extended query information Address Amax-A0 39h 3Ah 3Bh 3Ch 3Dh Data (hex) 50 52 49 31h 31h P R Y Common Flash interface (CFI) Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h Description Query ASCII string - extended table Major revision number Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) bit1, Suspend Erase supported (1=yes) bit2, Suspend Program supported (1=yes) bit3, Lock/Unlock supported (0=no) bit4, Queue Erase supported (0=no) bit5, Instant individual block locking (0=no) bit6, Protection bits supported (0=no) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) Bit 9, Reserved (P+5)h 3Eh 86h (P+6)h (P+7)h (P+8)h (P+9)h (P+A)h-(P+D)h (P+13)h-(P+40)h (P+41)h (P+42)h (P+43)h (P+44)h 3Fh 40h 41h 42h 43h-46h 4Ch-7Fh 80h 81h 82h 83h 01h 00h 00h 01h Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use Reserved Reserved xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh Unique device ID - 1 (16 bits) Unique device ID - 2 (16 bits) Unique device ID - 3 (16 bits) Unique device ID - 4 (16 bits) Synchronous Read supported 83/87 Common Flash interface (CFI) Table 35. Protection register information M58BW16F, M58BW32F Data Address A0-Amax M58BW16FT M58BW32FT M58BW16FB M58BW32FB 0x02 0x02 0x01 0xFE 0x01 0xFE 0x0 0x0 0x01 0x01 0x01 0xFE 0x01 0xFE 0x0 0x0 Value Instruction M58BW16FT M58BW16FB 2 x 64 Kb 2 x 64 Kb M58BW32FT M58BW32FB 1 x 128 Kb 1 x 128 Kb (P+E)h Number of Protection register field in JEDEC ID space, Block region information X256 bytes Protection field: this field describes user-available OTP Protection Register bytes. Bits 7-0=physical low address Bits 15-8=physical high address Bits 23-16='n', 2n=Factory preprogrammed bytes Bits 31-24='n', 2n=user programmable bytes (P+F)h (P+10)h (P+11)h - - x256 0x12 0x12 0x12 0x12 2 x 64 Kb 2 x 64 Kb 1 x 128 Kb 1 x 128 Kb 84/87 M58BW16F, M58BW32F Block protection Appendix C Block protection OTP protection The OTP protection is an user-enabled feature that permanently protects specific blocks, so called "OTP blocks", against modify operations (program/erase). It is available: on one specific 128-kbit parameter block in the M58BW32F- block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices on two specific 64-kbit parameter blocks in the M58BW16F- block 2 and 3 (01000h01FFFh) for bottom devices or block 36 and 35 (7E000h-7EFFFh) for top devices. The default state is unprotected. However, once the protection has been enabled, it is impossible to disable it and the OTP blocks will remain "modify protected" for ever. Obviously, this information is stored in internal non volatile registers. Activation sequence If the user wants to make the OTP protection effective on a part, he has to issue the Lock OTP protection command. The Lock OTP protection requires 2 write cycles: write (ADD=000AAh, DATA=49h) - Lock OTP Protection command 1 write (ADD=00003h, DATA=0000 0000h) - Lock OTP Protection command 2 This sequence of commands has to be given with the Tuning Protection unlocked (if this protection is enabled on the part) and with Write Protect Enable WP_N='1'. The user can check its execution polling on the SR in the same way as a normal Program Word command. The program duration lasts about 35 s like for a standard Program Word command. It is also possible to detect the end of the operation by polling the Status Register. Any Erase attempt returns A3h in the Status Register while any Program attempt returns 93h. Once the first write cycle of the Lock OTP protection command is issued, a wrong address on second write cycle will cause the activation sequence to fail. The Status Register allows detecting this event and its value is then B1h (invalid sequence). As a consequence, the protection is not active and the sequence must be restarted. The Lock OTP Protection command cannot be suspended. 85/87 Revision history M58BW16F, M58BW32F 10 Revision history Table 36. Date 09-Jun-2006 Document revision history Revision 1 Initial release. VPEN signal renamed as PEN and Program/Erase Enable (PEN) modified. Continuous burst and wrap options are not available, X-Latencies 7 and 8 removed (see Table 8: Burst Configuration Register and Table 9: Burst type definition). Notes removed below Table 8. tWHQV timing modified in Table 21: Asynchronous Write and Latch controlled Write AC characteristics. IDD max modified and IDD4 added to Table 18: DC characteristics. tAXQX modified in Table 20: Asynchronous Page Read AC characteristics. Read access specified in Asynchronous Bus Read and Synchronous Burst Read. tAVKH and tALKH added and tKHQV for 55 ns modified in Table 22: Synchronous Burst Read AC characteristics. Figure 9, Figure 10, Figure 18 and Figure 19 added. Double Word Program max modified and Minimum effective erase time added to Table 12: Program, Erase times and endurance cycles. All Asynchronous Bus Read AC characteristics brought together in Table 19: Asynchronous Bus Read AC characteristics. tLLEL removed from Table 19 and Figure 7. Appendix B: Common Flash interface (CFI) modified. Table 8: Burst Configuration Register, Table 30: CFI - device voltage and timing specification and Table 33: M58BW32F device geometry definition updated. Minimum values for tKHKL, tKLKH and tLLKH modified in Table 22: Synchronous Burst Read AC characteristics. tPHLL, tPHRH, tVDHPH, tWLRH, tGLRH, tELRH, and tLLRH added in Table 24: Reset, Power-down and Power-up AC characteristics. tPLRH removed from Table 24. Modified Figure 22: Reset, Power-down and Power-up AC waveforms - Control pins Low and Section 3.3.3: X-Latency bits (M13-M11). Appendix C: Block protection, Figure 23: Reset, Power-down and Power-up AC waveforms - Control pins toggling and Table 35: Protection register information added. Updated mechanical data of the LBGA package and Table 8: Burst Configuration Register, Table 12: Program, Erase times and endurance cycles, Table 18: DC characteristics, Table 21: Asynchronous Write and Latch controlled Write AC characteristics, Table 22: Synchronous Burst Read AC characteristics, and Section 2.7: Reset/Power-down (RP). Added Figure 21: Power supply slope specification and Table 23: Power supply AC and DC characteristics. Minor text changes. Applied Numonyx branding. Changes 23-Nov-2006 2 01-Oct-2007 3 15-Jan-2008 4 19-Mar-2008 5 86/87 M58BW16F, M58BW32F Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 87/87 |
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